Interfacing 8255 in mode 1

INTERFACING 8255 IN MODE 1

8255 mode 1 output configuration handshake transfer with control word format(image)

8255 MODE 1 OUTPUT CONFIGURATION HANDSHAKE TRANSFER WITH CONTROL WORD FORMAT

8255 mode 1 input configuration WITH handshake signal and control word format(image)

8255 MODE 1 INPUT CONFIGURATION AND CONTROL WORD FORMAT

8255 mode 2 bidirectional Input output(image)

8255 MODE 2 BIDIRECTIONAL INPUT OUTPUT

8259 Operating Modes

MODES OF 8259


1) FULLY NESTED MODE


This is a general purpose mode where all IR’s are arranged in highes to lowest.
IR0 highest and IR7 lowest.




2) AUTOMATIC ROTATION MODE


In this mode a device after being serviced receives the lowest priority.


3) SPECIFIC ROTATION MODE


In this user can select any IR for lowest priority thus fixing all priorities.

8259 Programmable interrupt controller

8259 Block diagram

READ/WRITE LOGIC


This is a typical read/write control logic. When A0 is low, the controller is selected 
to write a command. The chip select and A0 is used for determining port address.


CONTROL LOGIC


This has 2 pins INT(interrupt) and INTA(bar)(interrupt acknowledge) as input.
The INT is connected to MPU. Whereas the INTA(bar) is interrupt acknowledege 
from MPU.


INTERRUPT REGISTER AND PRIORITY RESOLVER


The interrupt request register(IRR) has 8 input lines. IR0 – IR7 for interrupts.
The request are stored in the register. 
The In service register(ISR) stores all levels that are currently being serviced. 
The interrupt mask register(IMR) stores the masking bits of interrupts lines to
be masked.
The priority resolver(PR) examines these registers and determines whether to send
INT to MPU or not.


CASCADED BUFFER/COMPARATOR


This is used to expand number of interrupts levels by cascading 2 or more 8259′s.

Write a subroutine in Assembly language to generate pulse every 50uS from counter 0 of 8254

; ASSUMPTION 8254 IS CONNECTED AT PORT 80H
; MEANING
; D7 D6 D5 D4 D3 D2 D1 D0
; 1 0 0 0 0 0 0 0
; HERE D1 -A1
; AND  D0 -A0
; WHERE A1 A0 ARE SELECTION LINES FOR COUNTER 0,1,2, AND CONTROL REGISTER
; SO 80H REFERS TO COUNTER 0
; 81H REFERS TO COUNTER 1
; 82H REFERS TO COUNTER 2
; 83H REFERS TO CONTROL REGISTER
; FOR SELECTION OF COUNTER 0


; SELECET LOAD COUNT MODE SELECTION 0,1,2 BINARY
; COUNTER 8-BIT 3,4, OR 5 COUNT
; D7 D6 D5 D4 D3 D2 D1 D0
; 0 0 0 1 0 1 0 0 FOR COUNTER 0
; 0 1 0 1 0 1 0 0 FOR COUNTER 1
; 1 0 0 1 0 1 0 0 FOR COUNTER 2
; WHICH GIVES US
; 14H
; 54H
; 94H
; 
;
; ASSUME 2MHZ FREQUENCY OF MPU
; THEREFORE CLOCK CYCLE = .5us
; NOW COUNT HERE TAKEN IS 8 BIT WHY??
; BECAUSE 
; COUNT = 50us/.5us = 100 = 64H
; PROGRAM GOES AS SHOWN


MVI A, 14H ; FOR COUNTER 0
OUT 83H ; WRITE TO CONTROL REGISTER
MVI A, 64H ; AS COUNT IS 8-BIT
OUT 80H ; LOAD COUNTER 0 WITH GIVEN
RET ; AS THIS IS A SUBROUTINE

8254 Operating Modes

8254 MODES

MODE 0: INTERRUPT ON TERMINAL COUNT

In this mode OUT is low. Once a count is loaded the counter is decremented after every cycle,

and when count reaches zero, the OUT goes high. 

This can be used as an interrupt. The OUT remains high until a new count or command word is 

loaded.

MODE 1: HARDWARE RETRIGGERABLE ONE SHOT

In this mode OUT is intially high. When gate is triggered, the OUT goes low, and at the end of

count it goes high again, thus generating a one shot pulse.

MODE 2: RATE GENERATOR

The mode is used to generate a pulse equal to given clock period at a given interval.

When a count is loaded, the OUT stays high until count reaches 1 and then OUT goes low

for 1 clock period then gets reloaded automatically and this is how pulse gets generated 

continuously.

MODE 3: SQUARE WAVE GENERATOR

In this a continuous square wave with period equal to count is generated. 

The frequency of square wave = frequency of clock divide by count.

if count (N) is odd pulse stay high for (N + 1)/2 and low for (N – 1)/2.

MODE 4: SOFTWARE TRIGGERED STROBE

In this mode OUT is initially high, it goes low for one clock period at the end of count.

The count must be reloaded for subsequent outputs.

MODE 5: HARDWARE TRIGGERED STROBE

Same as MODE4 except that it is triggered by rising pulse at gate.

8254/8253 Programmable interval timer

SHORT DESCRIPTION


The 8254 includes 3 identical 16-bit counter that can operate independently in any one of the 6 modes.
This includes a Status read back Command that can latch the count and status of counter.

8254 Block Diagram Each counter has 2 input signals CLK and GATE and one output signal OUT. DATA BUS BUFFER This tri state 8-bit bidirectional buffer is connected to data bus of MPU. CONTROL LOGIC This section has 5 signals RD(bar)(Read) WR(bar)(Write) CS(bar)(Chip select) and address line A0 and A1. In peripheral I/O mode  RD(bar) – IOR(bar) WR(bar) – IOW(bar) In Memory mapped mode RD(bar) – MEMR(bar) WR(bar) – MEMW(bar) A0 and A1 decoded address A0 A1 Selection 0 0 Counter 0  0 1 Counter 1 1 0 Counter 2 1 1 Control Register

8279 Programmable Keyboard/display interface

Short Description
This is a hardware approach to interface a matrix keyboard and a multiplexed display.
The display can be set as a right entry or a left entry.

8279 Block Diagram

KEYBOARD SECTION


This sectio has 8 lines. RL0 – RL7. Plus 2 additional lines. Shift and CNTL/STB. The keys are automatically debounced and keyboard can operate in two modes:
>>two key lockout mode or
>>N-key rollover.
In two key lockout mode if 2 keys are pressed simultaneously only firstkey is recongnized.
In N key rollover mode, simultaneous keys are recongnized and stored in internal buffer: it can also
be set up so that no key is recongnized until only one key is remained pressed.


This has a FIFO RAM.
The status logic keeps track of number of entries and provides IRQ(interrupt request) signal when
FIFO is empty.


DISPLAY SECTION


This section has 8 output lines divided into 2 groups of 4. A0 – A3 and B0 – B3.
These lines can be used in both ways 8 lines or 2 sets of 4 lines.
The display can be blanked using BD line. The section has 16×8 display RAM.


SCAN SECTION


This section has scan counter and 4 scan lines. SL0 – SL3. These 4 scan lines can be 
decoded using a 4 – 16 decoder to generate 16 lines for scanning.
These 16 lines can be connected to rows of a matrix keyboard and digit driveers of multiplexed
display.


MPU INBTERFACE SECTION


This section has 8 bi directional lines. DB0 – DB7. 1 interrupt request line(IRQ). 
6 lines for interfacing including buffer address lines A0.


When A0 is high – signals are interpreted as control word or status.
When A0 is low – signal is interpreted as data.
IRQ goes high whenever data is ready to be loaded into MPU.


QUESTIONS FOR ABOVE CONTEXT
Q) List major components of 8279 and explain their function
Q) Explain block diagram of 8279.