|INTERFACING 8255 IN MODE 1|
MODES OF 8259
1) FULLY NESTED MODE
This is a general purpose mode where all IR’s are arranged in highes to lowest.
IR0 highest and IR7 lowest.
2) AUTOMATIC ROTATION MODE
In this mode a device after being serviced receives the lowest priority.
3) SPECIFIC ROTATION MODE
In this user can select any IR for lowest priority thus fixing all priorities.
|8259 Block diagram|
This is a typical read/write control logic. When A0 is low, the controller is selected
to write a command. The chip select and A0 is used for determining port address.
This has 2 pins INT(interrupt) and INTA(bar)(interrupt acknowledge) as input.
The INT is connected to MPU. Whereas the INTA(bar) is interrupt acknowledege
INTERRUPT REGISTER AND PRIORITY RESOLVER
The interrupt request register(IRR) has 8 input lines. IR0 – IR7 for interrupts.
The request are stored in the register.
The In service register(ISR) stores all levels that are currently being serviced.
The interrupt mask register(IMR) stores the masking bits of interrupts lines to
The priority resolver(PR) examines these registers and determines whether to send
INT to MPU or not.
This is used to expand number of interrupts levels by cascading 2 or more 8259′s.
; D7 D6 D5 D4 D3 D2 D1 D0
; 1 0 0 0 0 0 0 0
; HERE D1 -A1
; AND D0 -A0
; WHERE A1 A0 ARE SELECTION LINES FOR COUNTER 0,1,2, AND CONTROL REGISTER
; SO 80H REFERS TO COUNTER 0
; 81H REFERS TO COUNTER 1
; 82H REFERS TO COUNTER 2
; 83H REFERS TO CONTROL REGISTER
; FOR SELECTION OF COUNTER 0
; SELECET LOAD COUNT MODE SELECTION 0,1,2 BINARY
; COUNTER 8-BIT 3,4, OR 5 COUNT
; D7 D6 D5 D4 D3 D2 D1 D0
; 0 0 0 1 0 1 0 0 FOR COUNTER 0
; 0 1 0 1 0 1 0 0 FOR COUNTER 1
; 1 0 0 1 0 1 0 0 FOR COUNTER 2
; WHICH GIVES US
; ASSUME 2MHZ FREQUENCY OF MPU
; THEREFORE CLOCK CYCLE = .5us
; NOW COUNT HERE TAKEN IS 8 BIT WHY??
; COUNT = 50us/.5us = 100 = 64H
; PROGRAM GOES AS SHOWN
MVI A, 14H ; FOR COUNTER 0
OUT 83H ; WRITE TO CONTROL REGISTER
MVI A, 64H ; AS COUNT IS 8-BIT
OUT 80H ; LOAD COUNTER 0 WITH GIVEN
RET ; AS THIS IS A SUBROUTINE
The 8254 includes 3 identical 16-bit counter that can operate independently in any one of the 6 modes.
This includes a Status read back Command that can latch the count and status of counter.
This is a hardware approach to interface a matrix keyboard and a multiplexed display.
The display can be set as a right entry or a left entry.
|8279 Block Diagram|
This sectio has 8 lines. RL0 – RL7. Plus 2 additional lines. Shift and CNTL/STB. The keys are automatically debounced and keyboard can operate in two modes:
>>two key lockout mode or
In two key lockout mode if 2 keys are pressed simultaneously only firstkey is recongnized.
In N key rollover mode, simultaneous keys are recongnized and stored in internal buffer: it can also
be set up so that no key is recongnized until only one key is remained pressed.
This has a FIFO RAM.
The status logic keeps track of number of entries and provides IRQ(interrupt request) signal when
FIFO is empty.
This section has 8 output lines divided into 2 groups of 4. A0 – A3 and B0 – B3.
These lines can be used in both ways 8 lines or 2 sets of 4 lines.
The display can be blanked using BD line. The section has 16×8 display RAM.
This section has scan counter and 4 scan lines. SL0 – SL3. These 4 scan lines can be
decoded using a 4 – 16 decoder to generate 16 lines for scanning.
These 16 lines can be connected to rows of a matrix keyboard and digit driveers of multiplexed
MPU INBTERFACE SECTION
This section has 8 bi directional lines. DB0 – DB7. 1 interrupt request line(IRQ).
6 lines for interfacing including buffer address lines A0.
When A0 is high – signals are interpreted as control word or status.
When A0 is low – signal is interpreted as data.
IRQ goes high whenever data is ready to be loaded into MPU.
QUESTIONS FOR ABOVE CONTEXT
Q) List major components of 8279 and explain their function
Q) Explain block diagram of 8279.