|8259 Block diagram|
This is a typical read/write control logic. When A0 is low, the controller is selected
to write a command. The chip select and A0 is used for determining port address.
This has 2 pins INT(interrupt) and INTA(bar)(interrupt acknowledge) as input.
The INT is connected to MPU. Whereas the INTA(bar) is interrupt acknowledege
INTERRUPT REGISTER AND PRIORITY RESOLVER
The interrupt request register(IRR) has 8 input lines. IR0 – IR7 for interrupts.
The request are stored in the register.
The In service register(ISR) stores all levels that are currently being serviced.
The interrupt mask register(IMR) stores the masking bits of interrupts lines to
The priority resolver(PR) examines these registers and determines whether to send
INT to MPU or not.
This is used to expand number of interrupts levels by cascading 2 or more 8259’s.