Interfacing 8255 in mode 1

INTERFACING 8255 IN MODE 1
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8259 Operating Modes


MODES OF 8259


1) FULLY NESTED MODE


This is a general purpose mode where all IR’s are arranged in highes to lowest.
IR0 highest and IR7 lowest.




2) AUTOMATIC ROTATION MODE


In this mode a device after being serviced receives the lowest priority.


3) SPECIFIC ROTATION MODE


In this user can select any IR for lowest priority thus fixing all priorities.

8259 Programmable interrupt controller

8259 Block diagram



READ/WRITE LOGIC


This is a typical read/write control logic. When A0 is low, the controller is selected 
to write a command. The chip select and A0 is used for determining port address.


CONTROL LOGIC


This has 2 pins INT(interrupt) and INTA(bar)(interrupt acknowledge) as input.
The INT is connected to MPU. Whereas the INTA(bar) is interrupt acknowledege 
from MPU.


INTERRUPT REGISTER AND PRIORITY RESOLVER


The interrupt request register(IRR) has 8 input lines. IR0 – IR7 for interrupts.
The request are stored in the register. 
The In service register(ISR) stores all levels that are currently being serviced. 
The interrupt mask register(IMR) stores the masking bits of interrupts lines to
be masked.
The priority resolver(PR) examines these registers and determines whether to send
INT to MPU or not.


CASCADED BUFFER/COMPARATOR


This is used to expand number of interrupts levels by cascading 2 or more 8259’s.

Write a subroutine in Assembly language to generate pulse every 50uS from counter 0 of 8254

; ASSUMPTION 8254 IS CONNECTED AT PORT 80H
; MEANING
; D7 D6 D5 D4 D3 D2 D1 D0
; 1 0 0 0 0 0 0 0
; HERE D1 -A1
; AND  D0 -A0
; WHERE A1 A0 ARE SELECTION LINES FOR COUNTER 0,1,2, AND CONTROL REGISTER
; SO 80H REFERS TO COUNTER 0
; 81H REFERS TO COUNTER 1
; 82H REFERS TO COUNTER 2
; 83H REFERS TO CONTROL REGISTER
; FOR SELECTION OF COUNTER 0


; SELECET LOAD COUNT MODE SELECTION 0,1,2 BINARY
; COUNTER 8-BIT 3,4, OR 5 COUNT
; D7 D6 D5 D4 D3 D2 D1 D0
; 0 0 0 1 0 1 0 0 FOR COUNTER 0
; 0 1 0 1 0 1 0 0 FOR COUNTER 1
; 1 0 0 1 0 1 0 0 FOR COUNTER 2
; WHICH GIVES US
; 14H
; 54H
; 94H

;
; ASSUME 2MHZ FREQUENCY OF MPU
; THEREFORE CLOCK CYCLE = .5us
; NOW COUNT HERE TAKEN IS 8 BIT WHY??
; BECAUSE 
; COUNT = 50us/.5us = 100 = 64H
; PROGRAM GOES AS SHOWN


MVI A, 14H ; FOR COUNTER 0
OUT 83H ; WRITE TO CONTROL REGISTER
MVI A, 64H ; AS COUNT IS 8-BIT
OUT 80H ; LOAD COUNTER 0 WITH GIVEN
RET ; AS THIS IS A SUBROUTINE